The majority of present day integrated circuits (ICs) are implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs), or simply MOS transistors. A MOS transistor includes a gate electrode as a control electrode, and a pair of spaced apart source and drain electrodes. A control voltage applied to the gate electrode controls the flow of a current through a channel between the source and drain electrodes.
The complexity of ICs and the number of devices incorporated in ICs are continually increasing. As the number of devices in an IC increases, the size of individual devices decreases. Device size in an IC is usually noted by the minimum feature size; that is, the minimum line width or the minimum spacing that is allowed by the circuit design rules. As the semiconductor industry moves to a minimum feature size of 45 nanometers (nm) and even smaller, the gain of performance due to scaling becomes limited. As new generations of integrated circuits and the MOS transistors that are used to implement those ICs are designed, technologists must rely heavily on non-conventional elements to boost device performance.
The performance of a MOS transistor, as measured by its current carrying capability, is proportional to the mobility of a majority carrier in the transistor's channel. By applying an appropriate uniaxial stress to the channel of the MOS transistor, the mobility of the majority carrier in the channel can be increased which increases drive current thereby improving performance of the MOS transistor. For example, applying a compressive uniaxial stress to the channel of a P-channel MOS (PMOS) transistor enhances the mobility of majority carrier holes, whereas applying a tensile uniaxial stress to the channel of an N-channel MOS (NMOS) transistor enhances the mobility of majority carrier electrons. The known stress engineering methods greatly enhance circuit performance by increasing device drive current without increasing device size and device capacitance.
Stress applied along the channel of the MOS transistor can be increased by providing a stress liner layer over the transistor which imparts stress along the channel. For a given spacing or “repeat distance” between adjacent transistors, the amount of stress applied to the channel is roughly proportional to the thickness of the stress liner layer up to a certain limit, at which point the amount of stress remains substantially the same regardless of further increases in thickness of the stress liner layer. In other words, the amount of stress applied to the channel saturates after a certain thickness.
Ideally, the stress liner layer is deposited so that it conforms to the surface of the gate electrodes and surfaces between adjacent gate electrodes such that the stress liner layer includes canyon-like regions between adjacent gate electrodes. However, when the thickness of the stress liner layer is greater than a certain thickness, a phenomenon known as “bridging” can occur where the canyon-like regions “close” and are also filled by the stress liner material. In other words, when bridging occurs, the stress liner material bridges a gap between adjacent gate electrodes. Increasing the thickness of the stress liner layer beyond a thickness where bridging begins to occur is of little value, if any, since the amount of stress tends to saturate beyond this thickness. In other words, as the thickness of the stress liner layer increases to the point where bridging starts and the canyon-like regions between adjacent gate electrodes begin to close, increases in device performance due to the stress liner layer tend to saturate, and therefore, there is no reason to increase the thickness of the stress liner layer beyond a certain thickness. Bridging becomes particularly problematic as the “gate pitch” or repeat distance between gate electrodes of adjacent MOS transistors decreases, which is desirable when attempting to decrease layout area. To help avoid bridging of the stress liner layer, one approach is to simply reduce the thickness of the stress liner layer.
Some integrated circuits include both narrow gate pitch transistors and wide gate pitch transistors. Narrow gate pitch transistors have a gate pitch which is less than that of the wide gate pitch transistors. Wide gate pitch transistors are generally provided in such a semiconductor device to provide transistors with improved performance in comparison to narrow gate pitch transistors. Wide gate pitch transistors have more stress line material between adjacent gate electrodes and this allows for a higher level of stress to be applied along the channels of these wide pitch transistors. With respect to wide gate pitch transistors, the thickness of the stress liner layer that can be deposited before bridging occurs is substantially greater since the spacing between adjacent gate electrodes is greater for wide gate pitch transistors. Therefore more stress liner material can be applied over the wide gate pitch transistors before the gap between adjacent gate electrodes is bridged by the stress liner layer. This helps to increase stress applied to the channel of the wide gate pitch transistors. However, when the narrow gate pitch transistors are also present, the thickness of the stress liner layer can not be increased too much since it would cause bridging with respect to the narrow gate pitch transistors.
Accordingly, it is desirable to provide improved methods for fabricating a stress enhanced semiconductor device which includes both narrow gate pitch transistors and wide gate pitch transistors. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.